1. Field of the Invention
The present invention relates to a semiconductor memory device and, particularly, a semiconductor memory device having a precharge circuit for precharging bit lines to a predetermined voltage.
2. Description of the Related Art
The field of use of the semiconductor memory device has been widened recently and semiconductor memory devices have been used in various electronic devices such as personal computers, television receivers and portable telephone sets. Although power source voltages of these electronic devices had been mainly 5 V, power source voltage is becoming as low as 2 to 3 V with the recent popularization of portable telephone set. Therefore, the recent semiconductor memory device is requested to operate within a power source voltage range as wide as 1.8 V to 5 V. The semiconductor memory device may include various memories such as read-only memory (ROM), write/read memory such as dynamic random access memory (DRAM) and static random access memory (SRAM) and memories such as erasable programmable ROM (EPROM) and electrically erasable PROM (EEPROM) which can hold stored information even when a power source is disconnected. Particularly, since an information stored in the SRAM among them is read out by using two complementary signal lines (bit lines), it is possible to read out the information relatively stably even if a power source voltage is varied.
In the ROM or the EPROM, however, it is usual that only one bit line is provided for every memory cell row. A sense amplifier is connected to the bit line and the sense amplifier amplifies a small signal read out from a memory cell and recovers an originally stored information "0" or "1". In such sense amplifier, in order to determine whether the stored information is "0" or "1", the stored information read out from a memory cell is compared with a certain reference. Therefore, although there is no problem when both the memory cell side and the reference side vary similarly with respect to a voltage variation, it becomes impossible to restore the originally stored information if the degree of variation of the characteristics of one side is different from that of the other side.
Japanese Patent Application Laid-open No. Hei 7-130189 discloses a semiconductor memory device capable of solving the above problem. The disclosed semiconductor memory device will be referred to as "prior art 1", hereinafter. According to the prior art 1, the voltage operation range of a sense amplifier circuit is expanded so that a normal read operation is possible even at low voltage. That is, in the prior art 1, a bias circuit composed of a precharge circuit for precharging a common data line connected to a plurality of data lines through respective selector switches and switch means for controlling precharge current is provided and, when a power source voltage is lowered, the precharge current is restricted.
The ROM is used mainly to read out a specific data stored therein and a data write can be done only once usually. Even when it is possible to write data therein a plurality times, it takes a relatively long time. For example, in an ROM, a program is performed by writing a specific data requested by a user in a mask used during a fabrication of a wafer thereof. An nMOS transistor is usually used as a memory cell constituting a mask ROM and a voltage sense type read circuit or a current sense type read circuit is used to read a data of the memory cell.
In the prior art 1, the sense amplifier is of the current sense type. Since the current sense type sense amplifier the originally stored information is determined by detecting a current variation of the bit line, sense time required for the determination does not depend on a discharge rate and so the data can be read out at high rate. However, in order to obtain a high rate read out, a large current is necessary, resulting in increased power consumption. Therefore, in an electronic device such as a portable telephone set which is driven by a battery, the lifetime of the battery is shortened. The voltage sense type sense amplifier is preferable in reducing the power consumption of the sense amplifier.
FIG. 7 is a block diagram showing a general construction of the voltage sense type semiconductor memory device. The semiconductor memory device shown in FIG. 7 comprises a memory cell array 701 and a peripheral circuit portion 702.
The peripheral circuit portion 702 includes an X decoder 703 inputted with an X address, a Y decoder 704 inputted with a Y address, a data latch circuit portion 706 for reading out data from a specific memory cell specified by the X address and the Y address and a timing generator circuit 705 responsive to an external clock signal and a control signal, for generating an internal clock signal including a precharge signal and a sampling clock signal.
FIG. 8 is a block diagram showing a construction of the data latch circuit portion 706 and the memory cell array 701 of the prior art 2. The memory array 701 is constructed with a plurality of memory blocks arranged in a matrix and each memory block is constructed with memory cells m1 to m4 and a selector transistor S. The selector transistor s and the memory cells ml to m4 are connected in series on sub bit line SubBL and a source of the memory cell m4 is grounded. The memory block is selected by a bit line BL in column direction and by a word line WL and a selection line SL in row direction. The data latch circuit portion 706 is constructed with precharge transistors Q1 to Qn, sense amplifiers SA1 to SAn and latch circuits L1 to Ln, which are arranged correspondingly to bit lines BL1 to BLn arranged for respective rows of the memory array 701.
In reading out data from the memory cell, the precharge transistors Q1 to Qn are initially turned on simultaneously in response to a precharge signal /PR generated by the timing generator circuit 705 to precharge the respective bit lines BL1 to BLn to a predetermined potential Vref, where symbol "/" of /PR is a bar and /PR indicates an active low signal. In this example, threshold voltages of the transistors Q1 to Qn are commonly 0V and the gate voltages Vref are output at sources thereof as they are.
Then, in a data read period, one of the selection lines SL specified by the X address in the memory cell array becomes "1" and a corresponding memory block is selected. One of the word lines WL connected to the selected memory block, which is specified by the X address, becomes "0" and the remaining word lines become "1". The word lines WL are connected to gates of the memory cells and a memory cell and a selection transistor whose word line WL and selection line SL become "1" is turned on.
The memory cell whose word line WL becomes "0" determines whether or not a current flows therethrough depending upon a memory content thereof. When a current flows through the selected memory cell, precharged charge is discharged through the selection transistor S and the memory cells m1 to m4. Therefore, the potential of the bit line BL is changed to L. On the contrary, when there is no current flowing through the selected memory cell, the precharged charge is held as it is and, therefore, the potential of the bit line BL is kept at H. This potential is judged by the sense amplifier SA and signals which are "H" or "L" at an edge of the sampling clock CLK are latched by the respective latch circuits L1 to Ln and outputted externally through the data bus.
FIG. 9(a) shows a detailed precharge signal generator portion of the timing generator circuit 705 shown in FIG. 7. The precharge signal generator portion is constructed with an analog delay circuit composed of a plurality of series connected inverters 901 for obtaining a desired delay time and an OR gate 902.
Odd numbered inverters of the series connected inverters 901 have one threshold voltages and even numbered inverters have another threshold voltages, so that the delay time of each inverter stage becomes large. Outputs of the odd numbered inverters fall in response to a rising edge of the sampling clock CLK and outputs of the even numbered inverters rise, while the outputs of the odd numbered inverters rise in response to a falling edge of the sampling clock CLK and those of the even numbered inverters fall.
FIG. 9(b) shows a timing chart of the precharge signal /PR. The precharge signal /PR is generated by an OR operation of the input clock signal CLK and a delay signal DEL. In order to design the inverters 901 such that an optimal delay time is obtained at high power source voltage Vdd, for example, 5 V, the threshold value of each inverter stage may be set 4 V or 1 V. When the power source voltage is lowered to 2 V under this condition, an output of a preceding inverter does not exceed the threshold value of a succeeding inverter and, therefore, the series connected inverters 901 does not work. On the other hand, since the threshold value of the OR gate 902 is set to a half of the power source voltage, the precharge signal generator portion operates even when the power source voltage becomes 2 V. Therefore, a signal which is substantially the same as the sampling clock CLK is output as the precharge signal /PR.
On the contrary, if the series connected inverters 901 are designed such that the optimal delay time is obtained at low power source voltage vdd, for example, 2 V, threshold value of each inverter stage may be set to 1.5 V or 0.8 V. When the power source voltage is increased to 5 V under this condition, an output of a preceding inverter immediately exceeds the threshold value of a succeeding inverter and, therefore, it becomes impossible to obtain enough delay time. Even if an OR operation of such delay time and the sampling clock CLK is performed, a time period in which the precharge signal /PR is L becomes very short.
FIG. 9(c) shows a circuit construction of each of the identical sense amplifiers SA1 to SAn. Taking the sense amplifier SA1 as an example, it is constructed with series connected inverters 801 and 802 connected between the latch circuit L1 and the transistor Q1 and a PMOS transistor 803 having a source-drain circuit connected between an input of the inverter 801 and a power source line supplying the power source voltage and a gate supplied with the precharge signal /PR. The PMOS transistor 803 of the sense amplifier SA1 becomes conductive when the precharge signal /PR becomes active, that is, when it becomes low level, to precharge the bit line BL1 up to the reference voltage Vref through the PMOS transistor Q1. Thereafter, the sense amplifier SA1 operates such that an output thereof becomes high level or low level correspondingly to a variation of the potential of the bit line through a circuit composed of the inverters 801 and 802 when the precharge signal /PR becomes inactive, that is, high level. In this example, it is assumed that a current supply function is smaller than that of the PMOS transistor 801, the selection transistor SL and the transistors m1 to m4 constituting the memory cells.
FIG. 10(a) shows a signal timing chart in precharging operation when the power source voltage is normal in the conventional semiconductor memory device, FIG. 10(b) shows a signal timing chart of a semiconductor memory device designed for high power source voltage when the power source voltage is lowered and FIG. 10(c) shows a signal timing chart of a semiconductor memory device designed for low power source voltage when the power source voltage is increased. In each of FIGS. 10(a), 10(b) and 10(c), it is assumed that a content of a memory cell in a first read cycle is "0" (ON) and that in a second read cycle is "1" (OFF).
In FIG. 10(a), a bit line BL is precharged up to a reference voltage Vref in a time period (tp) in which the precharge signal /PR is active and normally discharged in a sampling time period (ts), so that the sense amplifier correctly recognize "H" or "L" state of the bit line. It should be noted here that an address supply to the memory cell is performed in response to the rise of the precharge signal /PR.
In FIG. 10(b), when the power source voltage is reduced, a pulse width of the precharge signal /PR is broadened and the precharge time period (tp) becomes longer. Therefore, the charge on the bit line can not be discharged enough during the sampling time period (ts) of the first read cycle performed in response to the address supply in response to the rise of the precharge signal /PR, so that the voltage of the bit line can not be lowered down below the threshold voltage Vth of the precharge transistors (Q1 to Qn). Therefore, even if the information stored in the selected memory cell is "0" (ON), it is judged as "1" (OFF) erroneously.
In FIG. 10(c), the output of the OR gate 902 of the precharge signal generator portion becomes narrower than the desired output pulse width (tp) of the precharge signal /PR. Therefore, the bit line is not charged enough during the precharge time period (tp) and the potential of the bit line is lowered down below the threshold voltage Vth of the precharge transistor (Q1 to Qn), so that, even if the information stored in the selected memory cell is "1", it is judged as "0", erroneously.
As mentioned above, the power source voltage for the semiconductor memory device is becoming lowered and the semiconductor memory device is requested to operate with the power source voltage in the range as wide as from 1.8 V to 5 V. In order to obtain the semiconductor memory device operable in such wide power source voltage range, it is necessary to solve the problem of erroneous detection of signal on the bit line due to the width of the precharge signal generated by the timing generator circuit portion.